 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX21A IS
PORT ( ain  :  IN STD_LOGIC_VECTOR(4 DOWNTO 0);
       bin  :  IN STD_LOGIC_VECTOR(4 DOWNTO 0);
       cin  :  IN STD_LOGIC_VECTOR(4 DOWNTO 0);
       set  :  IN STD_LOGIC_vector(3 downto 0);
       y    :  OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END ENTITY MUX21A;
ARCHITECTURE ART OF MUX21A IS
             BEGIN
          
                   y<=ain WHEN set="0001"  else
                      bin when set="0010"  else
                      cin ;
          END ARCHITECTURE ART;
